Field of the Invention
The present invention relates to a voltage regulator configured to generate a constant output voltage Vout in response to an input voltage, and more specifically to output voltage accuracy of the voltage regulator.
Background Art
Generally, a voltage regulator generates a constant output voltage Vout at an output terminal in response to a power supply voltage VDD. The voltage regulator supplies current according to a load fluctuation and always keeps the output voltage Vout constant.
FIG. 4 is a circuit diagram of a related art voltage regulator. The related art voltage regulator is equipped with a reference voltage circuit 103, an error amplifier 104, an NMOS transistor 109, resistors 105 and 106, a capacitor 301, a power supply terminal 101, a ground terminal 100, and an output terminal 102.
When a reference voltage Vref of the reference voltage circuit 103 is larger than a divided voltage Vfb obtained by dividing an output voltage Vout of the output terminal 102 by the resistors 105 and 106, the output of the error amplifier 104 becomes high to reduce an on resistance of the NMOS transistor 109. Further, the voltage regulator is operated so as to raise the output voltage Vout and equalize the divided voltage Vfb and the reference voltage Vref to each other. When the reference voltage Vref is smaller than the divided voltage Vfb, the output of the error amplifier 104 becomes low to make high the on resistance of the NMOS transistor 109. Further, the voltage regulator is operated so as to reduce the output voltage Vout and equalize the divided voltage Vfb and the reference voltage Vref to each other.
The voltage regulator always keeps the divided voltage Vfb and the reference voltage Vref equally and thereby generates a constant output voltage Vout (refer to, for example, FIG. 5 in Patent Document 1)
[Patent Document 1]
Japanese Patent Application Laid-Open No. Hei 5 (1993)-127763